How To Use JadeChip for EDA in 10 Steps
Leverage Empyrean’s investment to close EDA gaps, boost Huawei‑compatible designs, and stay ahead in the chip race
The chip race is heating up, and Empyrean’s stake in JadeChip gives designers a powerful new toolset. By mastering JadeChip today, you can align your designs with Huawei’s 7nm standards and reduce time‑to‑market. This guide walks you through the exact steps to get started and optimize your EDA workflow.
Step 1: Set Up Your JadeChip Account
Create an account on the official JadeChip portal (www.jadechip.com) and verify your email. Download the free trial of JadeChip’s EDA suite and install the required libraries. Make sure your OS meets the minimum spec: 64‑bit Windows 10 or Ubuntu 20.04, 16GB RAM, 200GB SSD.
Step 2: Import Existing Design Files
Use the JadeChip Import Wizard to bring in your existing GDSII or OASIS files from Cadence or Synopsys. The wizard automatically maps layers and generates a design hierarchy. Verify the import with KLayout’s preview to catch any mismatches.
Step 3: Apply Huawei Tau Scaling Law Settings
Navigate to the "Scaling" tab in JadeChip and select the Huawei Tau Scaling Law preset. This automatically adjusts transistor sizing and interconnect spacing based on the latest 7nm data. Save the configuration as a template for future projects.
Step 4: Run Design Rule Check (DRC)
Launch JadeChip’s DRC engine, choosing the "Advanced" mode for stricter checks. The engine will flag violations like minimum width, spacing, and via size. Fix issues directly in the integrated editor and re‑run DRC until 0 violations remain.
Step 5: Perform Layout Versus Schematic (LVS)
Connect your schematic from Mentor Graphics PADS to JadeChip by exporting the netlist. The LVS tool will compare connectivity and identify mismatches. Use the "Auto‑Fix" feature to resolve common pin mapping errors.
Step 6: Optimize Power Delivery Network
Open the Power Planner module and load the design’s power grid. JadeChip’s AI optimizer will suggest via placements and metal widths to reduce IR drop below 20mV. Export the updated power grid and re‑run DRC to confirm compliance.
Step 7: Simulate Timing with JadeChip Timing Analyzer
Import the post‑layout netlist into JadeChip’s Timing Analyzer. Set the target clock frequency (e.g., 1.2GHz) and run a static timing analysis. The tool will highlight critical paths and suggest buffer insertion points.
Step 8: Generate GDSII for Fabrication
Once all checks pass, use the "Export GDSII" function. Include the Huawei‑specific mask layers required for 7nm process. Validate the final GDSII with a third‑party viewer like GDSII Viewer to ensure no missing layers.
Step 9: Integrate with Empyrean’s Cloud Service
Upload the GDSII to Empyrean’s secure cloud via the API endpoint https://api.empyrean.com/v1/upload. Use the provided OAuth token and set the project ID. This enables real‑time collaboration with Huawei’s design team.
Step 10: Track Project Metrics with JadeChip Dashboard
Log into the JadeChip dashboard to view key metrics: DRC violation count, timing slack, power consumption, and cost estimates. Set up email alerts for any threshold breaches. Export the report as PDF for stakeholder meetings.
Many designers overlook the importance of early power grid optimization; doing it before DRC can save hours of re‑work.
You’ve now learned how to harness JadeChip’s capabilities to accelerate EDA projects and align with Huawei’s standards. By following these steps, you’ll reduce design cycle time and improve manufacturability. Next, share your optimized GDSII with the fabrication house and monitor the production metrics through the JadeChip dashboard.
